1. Field of the Invention
The present invention generally relates to a method of manufacturing the MOSFET (metal oxide semiconductor field effect transistor). More particularly, the present invention relates to a method for fabricating a power MOSFET.
2. Description of Related Art
A power MOSFET can be used to amplify the power, handling the high voltage and the high electric current of the semiconductor devices. The following FIG. 1A to FIG. 1G will explain the prior procedures in fabricating a power MOSFET.
Firstly, referring to the FIG. 1A, a silicon oxide gate dielectric layer 104 and a polysilicon gate layer 106 are formed over a substrate 100 comprising an epitaxial layer 102.
Then, referring to the FIG. 1B, through the process of photolithography and etching, the polysilicon gate layer 106 and the silicon oxide gate dielectric layer 104 are defined to form a gate structure 105. Then, the ion implantation process is carried to form a well region 110 inside the epitaxial layer 102.
Afterwards, further referring to the FIG. 1C, the photoresist layer 112 is formed over the substrate 100 by using spin coating. After the processes of exposure and development, the photoresist layer 112 is patterned to form the patterned photoresist layer 112a as presented in FIG. 1D.
Referring to the FIG. 1E, the patterned photoresist 112a is used as an implanted mask for ion implantation to form a source region 114 inside the well region 110, and then the patterned photoresist layer 112a is removed.
According to the FIG. 1F, a patterned photoresist 116 is formed upon the substrate 100 to cover the gate structure 105 and the source region 114 and expose the surface of the well region 110 that is preserved for the body region. Then the patterned photoresist 116 is used as a mask for ion implantation to form the body region 118 inside the well region 110.
Finally, referring to 1G, a dielectric layer 120 is formed over the substrate 100 to cover the gate structure 105, the source region 114 and the body region 118 after the removal of the patterned photoresist 116. Then, the photolithography and etching processes are performed to form a contact opening 122 in the dielectric layer 120.
From the above mentioned procedures, several photoresist layers are required to define the underneath layer in order to form the gate structure 105, source region 114, body region 118, contact opening 122. That is, for each of these fabrication processes, a photolithography process is needed. Hence, for the common fabrication procedures, at least 5 to 6 photolithography processes are required. However, such complicated procedures will increase the demand for the manpower and the fabrication of the masks cause high costs, not beneficial for cost reduction.
Besides, during the previously mentioned process for forming the source region 114, it is necessary to form the patterned photoresist layer 112a over the substrate 100 (as shown in FIG. 1D) and as mask to enable the ion implantation procedure for forming the source region 114 (as shown in FIG. 1E). However, as the integration of electric devices becomes higher, the critical dimension (CD) becomes smaller. Deviation of the resultant patterns may occur, while the small size of the patterned photoresist layer 112a causes collapse or even peeling for the patterned photoresist layer 112a. Besides, during the formation of source region 114, the patterned photoresist layer 112a is easily damaged by the high current implantor from the ion implantation process, which may result in the imprecise definition.
In addition, during the process to define the photoresist layer 112 in order to form the patterned photoresist layer 112a, if the patterned photoresist 112a for exposing the preserved body region is misaligned, the resultant source region 114 will become asymmetric, thus affecting the following processes.
Furthermore, misalignment can happen during the process for forming the contact opening 122 and consequently causes abnormal electrical connection for transistors, so that the electrical reliability of the devices will decrease.